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| a FEATURES 1.5% Accuracy Over Line, Load and Temperature Low 800 A (Typical) Quiescent Current Shutdown Current: 1 A (Typical) Stable with 10 F Load Capacitor +2.5 V to +15 V Operating Range Fixed Output Voltage Options: 2.8 V, 3 V, 3.3 V, 5 V Up to 10 A Output Current SO-8 Package -40 C to +85 C Ambient Temperature Range Internal Gate to Source Protective Clamp Current and Thermal Limiting Programmable Current Limit Foldback Current Limit APPLICATIONS Desktop Computers Handheld Instruments Cellular Telephones Battery Operated Devices Solar Powered Instruments High Efficiency Linear Power Supplies Battery Chargers VIN + EN BIAS Precision Voltage Regulator Controller ADP3310 FUNCTIONAL BLOCK DIAGRAM VIN + ADP3310 - 50mV IS VREF GATE VOUT GND RS 50mV NDP6020P VOUT + 10 F - GENERAL DESCRIPTION 1F - The ADP3310 is a precision voltage regulator controller that can be used with an external Power PMOS device such as the NDP6020P to form a two chip low dropout linear regulator. The low quiescent current (800 A) and the Enable feature make this device especially suitable for battery powered systems. The dropout voltage at 1 A is only 70 mV when used with the NDP6020P, allowing operation with minimal headroom and prolonging battery useful life. The ADP3310 can drive a wide range of currents, depending on the external PMOS device used. Additional features of this device include: high accuracy ( 1.5%) over line, load and temperature, gate-to-source voltage clamp to protect the external MOSFET and foldback current limit. A current limit threshold voltage of 50 mV (typ) allows 50 m of board metal trace resistance to provide a 1 A current limit. The ADP3310 operates from a wide input voltage range from 2.5 V to 15 V and is available in a small SO-8 package. IS VIN EN GATE VOUT ON OFF ADP3310 GND Figure 1. Typical Application Circuit REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 1999 ADP3310-SPECIFICATIONS (V Parameter OUTPUT VOLTAGE ACCURACY (Figure 1) QUIESCENT CURRENT Shutdown Mode Normal Mode GATE TO SOURCE CLAMP VOLTAGE GATE DRIVE MINIMUM VOLTAGE GATE DRIVE CURRENT (SINK/SOURCE) V GS GAIN V OUT IN = VOUT + 1 V, TA = -40 C to +85 C unless otherwise noted) Symbol Min Typ Max Units Conditions VIN = VOUT +1 V to 15 V VEN = 2 V, IOUT = 10 mA to 1 A VEN = 0 V VEN = 2 V, IOUT = 500 A VOUT = 0 V, VIN = 15 V VOUT IGND IGND -1.5 1 800 8 0.7 1 80 +1.5 10 1000 10 % A A V V mA dB CURRENT LIMIT THRESHOLD VOLTAGE LOAD REGULATION LINE REGULATION SHUTDOWN INPUT VOLTAGE SHUTDOWN INPUT CURRENT Specifications subject to change without notice. VIN - VIS IOUT = 10 mA to 1 A VIN = VOUT +1 V to 15 V IOUT = 100 mA VIH VIL VEN = 0 V to 5.0 V VEN IEN 40 -10 -10 2.0 50 80 10 10 0.4 mV mV mV V V A -10 +10 ABSOLUTE MAXIMUM RATINGS* Input Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . +20 V Enable Input Voltage . . . . . . . . . . . . . . . 0.3 V to V IN + 0.3 V Operating Junction Temperature Range . . . -40C to +125C Operating Temperature Range . . . . . . . . . . . -40C to +85C Storage Temperature Range . . . . . . . . . . . . -65C to +150C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . +300C Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . +215C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +220C JA (4-Layer Board) . . . . . . . . . . . . . . . . . . . . . . . . +121C/W JA (2-Layer Board . . . . . . . . . . . . . . . . . . . . . . . . . +150C/W *This is a stress rating only; operation beyond these limits can cause the device to be permanently damaged. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADP3310 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE -2- REV. A ADP3310 ORDERING GUIDE Model ADP3310AR-2.8 ADP3310AR-3 ADP3310AR-3.3 ADP3310AR-5 Output Voltage 2.8 V 3V 3.3 V 5V Package Option* SO-8 SO-8 SO-8 SO-8 PIN CONFIGURATION SO-8 IS 1 NC 2 8 EN 7 GND TOP VIEW GATE 3 (Not to Scale) 6 NC VIN 4 5 VOUT ADP3310 *SO = Small Outline. Contact the factory for the availability of other output voltage options from 5 V to 16.5 V. Refer to the ADP3319 data sheet for 1.8 V and 2.5 V output voltage options. Refer to the ADP3328 data sheet for adjustable output version. NC = NO CONNECT PIN FUNCTION DESCRIPTIONS Pin SO-8 1 Name IS Function Current Sense. Connected to the more negative terminal of the sense resistor as well as the Power MOSFET's source pin. IS must be tied to VIN pin if the current limit feature is not used. No Connect. Gate Drive for the external MOSFET. Input Voltage. This is also the positive terminal connection of the current sense resistor. Output Voltage Sense. This pin is connected to the MOSFET's drain and directly to the load for optimal load regulation. Bypass to ground with a 10 F or larger capacitor. Device Ground. This pin should be tied to system ground closest to the load. Enable. Pulling this pin to a logic High or tying the pin to the input voltage will enable the output. Pulling this pin low will disable the regulator output. 2, 6 3 4 NC GATE VIN 5 VOUT 7 8 GND EN Table I. Alternate PMOS Devices PMOS Manufacturer RDS(ON) ID Continuous @ 25C PD @ 25C Derating Factor Package NDP6020P Fairchild 0.075 @ VGS = -2.5 V -27 A @ VGS = -4.5 V 75 W 0.5 W/C TO-220 IRF7404 IR 0.06 @ VGS = -2.7 V -5.3 A @ VGS = -4.5 V 1.6 W 0.011 W/C SO-8 Si9434DY Temic 0.06 @ VGS = -2.5 V -6.4 A 2.5 W 1.6 W @ 70C SO-8 REV. A -3- ADP3310 -Typical Performance Characteristics (Circuit of Figure 1) 3.310 VIN = 5V 1.6 ILOAD = 10mA 1.4 1.2 1.0 0.8 0.6 3.295 0.4 0.2 3.290 0.001 0 3.5 3.305 3.300 IGND - mA VOUT - V 0.01 0.1 0 10 ILOAD - mA 100 1000 5.5 7.5 9.5 VIN - V 11.5 13.5 15.5 Figure 2. VOUT vs. ILOAD (V IN = 5 V) Figure 5. I GND vs. VIN (ILOAD = 10 mA) 3.310 ILOAD = 1A 2.0 ILOAD = 1A 1.8 1.6 3.305 1.4 IGND - mA VOUT - V 1.2 1.0 0.8 0.6 3.300 3.295 0.4 0.2 3.290 3.5 5.5 7.5 9.5 VIN - V 11.5 13.5 15.5 0 3.5 5.5 7.5 9.5 VIN - V 11.5 13.5 15.5 Figure 3. VOUT vs. VIN (ILOAD = 1 A) Figure 6. IGND vs. VIN (ILOAD = 1 A) 3.310 ILOAD = 10mA 1.2 VIN = 5V 1.1 3.305 1.0 IGND - mA 0.9 VOUT - V 3.300 0.8 0.7 3.295 0.6 3.290 3.7 0.5 0.001 4 4.5 5 7 VIN - V 9 11 13 15 0.01 0.1 1 ILOAD - mA 10 100 1000 Figure 4. VOUT vs. VIN (I LOAD = 10 mA) Figure 7. IGND vs. ILOAD (VIN = 5 V) -4- REV. A ADP3310 1.5 1.4 1.3 1.2 IGND - mA 1.1 1.0 0.9 0.8 0.7 0.6 0.5 -40 -20 0 20 40 TEMPERATURE - C 60 80 ILOAD 1A VIN = 5V ILOAD = 10mA 3.400 3.300 3.200 VIN = 5V CL = 10 F VOUT - V 10mA 250 s/DIV Figure 8. Quiescent Current vs. Temperature Figure 11. Load Transient Response 3.5 ILOAD = 10mA 3.0 2.5 2.0 1.5 1.0 0.5 0 0 2.0 2.8 5.0 VIN - V 2.8 2.0 0 PSRR - dB VOUT - V 0 -10 -20 -30 -40 -50 -60 -70 -80 CLOAD = 10 F ILOAD = 1mA 1 10 100 1k 10k FREQUENCY - Hz 100k 1M Figure 9. Power-Up/Power-Down Figure 12. Ripple Rejection 4.0 ILOAD = 10mA CL = 10 F VIN - V 7.0 3.0 5.5 VOUT - V 2.5 2.0 1.5 1.0 0.5 0 5ms/DIV 0 20 40 60 80 100 120 ILOAD - mA 140 160 180 3.5 VIN = 5V RCS = 0.50 3.32 VOUT - V 3.30 3.28 Figure 10. Line Transient Response--(10 F Load) Figure 13. Foldback Current REV. A -5- ADP3310 APPLICATION INFORMATION The ADP3310 is very easy to use. A P-channel power MOSFET and a small capacitor on the output is all that is needed to form an inexpensive ultralow dropout regulator. The advantage of using the ADP3310 controller is that it can drive a pass PMOS FET to provide a regulated output at high current. FET Selection VDSMAX = Maximum Drain to Source Voltage = Maximum Output Current IOMAX 125 - 50 = 14.7C/W JA = 1.7 x 3 For such a low JA, a P-channel FET from Fairchild, such as NDP6020P in a heatsink mountable TO-220 package, is required. The required external heatsink is determined as follows: CA CA JA JC JC CA = JA - JC = Case-to-Ambient Thermal Resistance = Junction-to-Ambient Thermal Resistance = Junction-to-Case Thermal Resistance = 2C/W for NDP6020P = 14.7C/W - 2C/W = 12.7C/W The type and size of the pass transistor are determined by the threshold voltage, input-output voltage differential and load current. The selected PMOS must satisfy the physical and thermal design requirements. Table I shows a partial list of manufacturers providing the PMOS devices. To ensure that the maximum VGS provided by the controller will turn on the FET at worst case conditions (i.e., temperature and manufacturing tolerances), the maximum available VGS must be determined. Maximum VGS is calculated as follows: (1) VGS = VIN - VBE - IOMAX x RS IOMAX = Maximum Output Current RS = Current Sense Resistor VBE ~ 0.7 V (Room Temp) ~ 0.5 V (Hot) ~ 0.9 V (Cold) For Example: VIN = 5 V, VO = 3.3 V and IOMAX = 3 A, VGS = 5 V - 0.7 V - 3 A x 11 m = 4.27 V Equation (1) applies to a gate-to-source voltage less than the gate to source clamp voltage. (2) VDS = VIN - VO VDS = 5 V - 3.3 V = 1.7 V If VIN 5 V, logic level FET should be considered. If VIN > 5 V, either logic level or standard MOSFET can be used. The difference between VIS and VOUT (VDS) must exceed the voltage drop due to the load current and the ON resistance of the FET. As a safety margin, it is recommended to use a MOSFET with a VGS at least 1.5 times lower than the calculated VGS value from Equation 1. Also, in the event the circuit is shorted to ground, the MOSFET must be able to conduct the maximum short circuit current. The selected MOSFET must satisfy these criteria; otherwise, a different pass device should be used. If the FET data is not available in the catalogue, contact the FET manufacturer. Thermal Design For a safety margin, select a heatsink with a CA less than half of the value calculated above to allow extended duration of short circuit. In a natural convection environment, a large heatsink such as 3" length of Type 63020 extrusion from Aavid Engineering is required. External Capacitors The ADP3310 is stable with virtually any good quality capacitors (anyCAPTM), independent of the capacitor's minimum ESR (Effective Series Resistance) value. The actual value of the capacitor and its associated ESR depends on the gm and capacitance of the external PMOS device. A 10 F capacitor at the output is sufficient to ensure stability for up to 10 A output current. Larger capacitors can be used if high output current surges are anticipated. Extremely low ESR capacitors (ESR0) such as multilayer ceramic or OSCON are preferred because they offer lower ripple on the output. For less demanding requirements, a standard tantalum or even an aluminum electrolytic is adequate. However, if an aluminum electrolytic is used, be sure it meets the temperature requirements because aluminum electrolytic has poor performance over temperature. Shutdown Mode Applying a TTL high signal to the EN pin or tying it to the input pin will enable the output. Pulling this pin low or tying it to ground will disable the output. In shutdown mode, the controller's quiescent current is reduced to less than 1 A. Gate-to-Source Clamp The maximum allowable thermal resistance between the FET junction and the highest ambient temperature must be taken into account to determine the type of FET package used. One square inch of PCB copper area as heatsink yields a typical JA ~ 60C/W for the SOT-223 package and JA ~ 50C/W for the SO-8 package. For substantially lower thermal resistances, D2PAK or TO-220 type of packages are recommended. For normal applications, the FET can be directly mounted to the PCB. But, for higher power applications, an external heat sink is required to satisfy the JA requirement and provide adequate heatsink. Calculating thermal resistance for VIN = 5 V, VO = 3.3 V, and IO = 3 A: JA = T J - TAMBMAX (V DSMAX x IOMAX ) An 8 V gate-to-source voltage clamp is provided to protect the MOSFET in the event the output is suddenly shorted to ground. This allows the use of the new, low on-state resistance (RDSON) FETs. Short Circuit Protection The power FET is protected during short circuit conditions with a foldback type of current limiting which significantly reduces the current. Current Sense Resistor Current limit is achieved by setting an appropriate current sense resistor (RS) across the current limit threshold voltage. Current limit sense resistor RS is calculated as follows: RS = 0.05 (1.5 x IO ) TJ = Junction Temperature TAMBMAX = Maximum Ambient Temperature -6- anyCAP is a trademark of Analog Devices, Inc. REV. A ADP3310 Current Limit Threshold Voltage = 0.05 V Safety Factor = 1.5 IO = Output Current RS is not needed in circuits that do not require current limiting. In that case, the IS pin must be tied to the input pin. The simplest and cheapest sense resistor for high current applications, (i.e., Figure 1) is a PCB trace. The temperature dependence of the copper trace and the thickness tolerances of the trace must be taken into account in the design. The resistivity of copper has a positive temperature coefficient of +0.39%/C. Copper's Tempco in conjunction with the proportional-toabsolute temperature (PTAT) current limit voltage can provide an accurate current limit. Table II provides the resistance value for PCB copper traces. Alternately, an appropriate sense resistor such as surface mount sense resistors available from KRL can be used. PCB-Layout Issues Table II. Printed Circuit Copper Resistance Conductor Thickness 1/2 oz/ft2 (18 m) Conductor Width In 0.025 0.050 0.100 0.200 0.500 0.025 0.050 0.100 50mV/div 0.200 0.500 0.025 0.050 0.100 0.200 0.500 0.025 0.050 0.100 0.200 0.500 R2 0.011 M1 NDP6020P Resistance m/In 39.3 19.7 9.83 4.91 1.97 19.7 9.83 4.91 5s/div 2.46 0.98 9.83 4.91 2.46 1.23 0.49 6.5 3.25 1.63 0.81 0.325 1 oz/ft2 (35 m) 2V/div 2 oz/ft2 (70 m) For optimum voltage regulation, place the load as close as possible to the device's VOUT and GND pins. It is recommended to use dedicated PCB traces to connect the MOSFET's drain to the positive terminal and GND to the negative terminal of the load to avoid voltage drops along the high current carrying PCB traces. Application Circuits Typical 3 A LDO Circuit 3 oz/ft2 (106 m) The ADP3310 and a power MOSFET can be used to power the new generation of CPUs and microprocessors from the standard +5 V supply at a very low cost (Figure 14). This circuit provides low dropout, fast switching and high switching load current from 0 A to 3 A. Due to the high switching load current, capacitors with high ripple current carrying capability, such as OSCON or special tantalum capacitors from Sprague (593D), are recommended for the output. 4.5V TO 5.5V 220 F OSCON + 10 F 1k + 10 F 3.3V 3 220 F OSCON IS VIN GATE ADP3310-3.3 EN GND VOUT Figure 14. Typical 3 A Low Dropout Regulator Circuit VIN = 5V TO 15V OSCON 220 F + CIN C1 1F ** COILTRONICS CTX-68-4 ** KRL SL-1-C1-ORO5OL MI IRF7404 C2 10nF VIN P-DRIVE INT VCC SD IRF7204 L* 68H C3 1nF RSENSE** OSCON 220 F 0.1 C4 R1 30.1k 1% IS IN EN GND 2N3906 Q2 GATE OUT BAT54 C5 10 F 3.3V/1A ADP1148 SENSE+ ITH RC 1k CC 22nF CT 470pF CT SENSE- N-DRIVE N-CH IRF7403 ADP3310-3.3 D1 10BQ040 2N3906 Q1 R2 124k 1% FB S-GND P-GND R3 274k Figure 15. High Current Post Regulator with SOIC PMOS REV. A -7- ADP3310 High Current Post Regulator with SOIC PMOS VOS In applications where cost is a higher concern than efficiency, a resistor divider can be used to provide feedback instead of the current mirror. Power efficiency is lower in cases of light loads. 20mV/div 5s Figure 16. Pre-and Post-Regulated Voltage OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 5mAOS 8-Lead Small Outline (SO-8) 0.1968 (5.00) 0.1890 (4.80) 8 5 4 5M55mV 0.1574 (4.00) 0.1497 (3.80) PIN 1 1 0.2440 (6.20) 0.2284 (5.80) 0.0500 (1.27) BSC 0.0098 (0.25) 0.0040 (0.10) SEATING PLANE 0.0688 (1.75) 0.0532 (1.35) 0.0192 (0.49) 0.0138 (0.35) 8 0.0098 (0.25) 0 0.0075 (0.19) 0.0196 (0.50) 0.0099 (0.25) 45 0.0500 (1.27) 0.0160 (0.41) -8- REV. A PRINTED IN U.S.A. C2982a-0-12/99 (rev. A) Post regulation for a switch-mode supply (Figure 15) can be implemented with a PMOS in an SO-8 package to provide a significant reduction in peak-to-peak ripple voltage. A constant dropout voltage in conjunction with low quiescent current yield a more efficient voltage regulator that can significantly extend battery life. The bottom waveform of Figure 16 is the output of the switching regulator. The top waveform is the output of the post regulator. 10mV/div VO |
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